SDR SDRAM Synchronous dynamic random-access memory

1 sdr sdram

1.1 sdram control signals

1.1.1 command signals
1.1.2 bank selection (ban)
1.1.3 addressing (a10/an)
1.1.4 commands


1.2 sdram construction , operation
1.3 command interactions

1.3.1 interrupting read burst


1.4 sdram burst ordering
1.5 sdram mode register
1.6 auto refresh
1.7 low power modes
1.8 ddr sdram prefetch architecture

sdr sdram

the 64 mb of sound memory on sound blaster x-fi fatality pro sound card built 2 micron 48lc32m8a2 sdram chips. run @ 133 mhz (7.5 ns clock period) , have 8-bit wide data buses.

originally known sdram, single data rate sdram can accept 1 command , transfer 1 word of data per clock cycle. typical clock frequencies 100 , 133 mhz. chips made variety of data bus sizes (most commonly 4, 8 or 16 bits), chips assembled 168-pin dimms read or write 64 (non-ecc) or 72 (ecc) bits @ time.

use of data bus intricate , requires complex dram controller circuit. because data written dram must presented in same cycle write command, reads produce output 2 or 3 cycles after read command. dram controller must ensure data bus never required read , write @ same time.

typical sdr sdram clock rates 66, 100, , 133 mhz (periods of 15, 10, , 7.5 ns). clock rates 200 mhz available.

sdram control signals

all commands timed relative rising edge of clock signal. in addition clock, there 6 control signals, active low, sampled on rising edge of clock:

cke clock enable. when signal low, chip behaves if clock has stopped. no commands interpreted , command latency times not elapse. state of other control lines not relevant. effect of signal delayed 1 clock cycle. is, current clock cycle proceeds usual, following clock cycle ignored, except testing cke input again. normal operations resume on rising edge of clock after 1 cke sampled high.put way, other chip operations timed relative rising edge of masked clock. masked clock logical , of input clock , state of cke signal during previous rising edge of input clock.
cs chip select. when signal high, chip ignores other inputs (except cke), , acts if nop command received.
dqm data mask. (the letter q appears because, following digital logic conventions, data lines known dq lines.) when high, these signals suppress data i/o. when accompanying write data, data not written dram. when asserted high 2 cycles before read cycle, read data not output chip. there 1 dqm line per 8 bits on x16 memory chip or dimm.

command signals

ras row address strobe. despite name, not strobe, rather command bit. along cas , we, selects 1 of 8 commands.
cas column address strobe. despite name, not strobe, rather command bit. along ras , we, selects 1 of 8 commands.
we write enable. along ras , cas, selects 1 of 8 commands. distinguishes read-like commands write-like commands.

bank selection (ban)

sdram devices internally divided either 2, 4 or 8 independent internal data banks. 1 3 bank address inputs (ba0, ba1 , ba2) used select bank command directed toward.

addressing (a10/an)

many commands use address presented on address input pins. commands, either not use address, or present column address, use a10 select variants.

commands

the commands defined follows:

all sdram generations (sdr , ddrx) use same commands, changes being:

additional address bits support larger devices
additional bank select bits
wider mode registers (ddr2 , use 13 bits, a0–a12)
additional extended mode registers (selected bank address bits)
ddr2 deletes burst terminate command; ddr3 reassigns zq calibration
ddr3 , ddr4 use a12 during read , write command indicate burst chop , half-length data transfer
ddr4 changes encoding of activate command. new signal act controls it, during other control lines used row address bits 16, 15 , 14. when act high, other commands same above.

sdram construction , operation

for example, 512 mb sdram dimm (which contains 512 mib (mebibytes) = 512 × 2 bytes = 536,870,912 bytes exactly), might made of 8 or 9 sdram chips, each containing 512 mbit of storage, , each 1 contributing 8 bits dimm s 64- or 72-bit width. typical 512 mbit sdram chip internally contains 4 independent 16 mb (mib) memory banks. each bank array of 8,192 rows of 16,384 bits each. (1024 16-bit columns). bank either idle, active, or changing 1 other.

the active command activates idle bank. presents two-bit bank address (ba0–ba1) , 13-bit row address (a0–a12), , causes read of row bank s array of 16,384 column sense amplifiers. known opening row. operation has side effect of refreshing dynamic (capacitive) memory storage cells of row.

once row has been activated or opened , read , write commands possible row. activation requires minimum amount of time, called row-to-column delay, or trcd before reads or writes may occur. time, rounded next multiple of clock period, specifies minimum number of wait cycles between active command, , read or write command. during these wait cycles, additional commands may sent other banks; because each bank operates independently.

both read , write commands require column address. because each chip accesses 8 bits of data @ time, there 2048 possible column addresses requiring 11 address lines (a0–a9, a11).

when read command issued, sdram produce corresponding output data on dq lines in time rising edge of clock few clock cycles later, depending on configured cas latency. subsequent words of burst produced in time subsequent rising clock edges.

a write command accompanied data written driven on dq lines during same rising clock edge. duty of memory controller ensure sdram not driving read data on dq lines @ same time needs drive write data on lines. can done waiting until read burst has finished, terminating read burst, or using dqm control line.

when memory controller needs access different row, must first return bank s sense amplifiers idle state, ready sense next row. known precharge operation, or closing row. precharge may commanded explicitly, or may performed automatically @ conclusion of read or write operation. again, there minimum time, row precharge delay, trp, must elapse before bank idle , may receive activate command.

although refreshing row automatic side effect of activating it, there minimum time happen, requires minimum row access time tras delay between active command opening row, , corresponding precharge command closing it. limit dwarfed desired read , write commands row, value has little effect on typical performance.

command interactions

the no operation command permitted, while load mode register command requires banks idle, , delay afterward changes take effect. auto refresh command requires banks idle, , takes refresh cycle time trfc return chip idle state. (this time equal trcd+trp.) other command permitted on idle bank active command. takes, mentioned above, trcd before row open , can accept read , write commands.

when bank open, there 4 commands permitted: read, write, burst terminate, , precharge. read , write commands begin bursts, can interrupted following commands.

interrupting read burst

a read, burst terminate, or precharge command may issued @ time after read command, , interrupt read burst after configured cas latency. if read command issued on cycle 0, read command issued on cycle 2, , cas latency 3, first read command begin bursting data out during cycles 3 , 4, results second read command appear beginning cycle 5.

if command issued on cycle 2 burst terminate, or precharge of active bank, no output generated during cycle 5.

although interrupting read may active bank, precharge command interrupt read burst if same bank or banks; precharge command different bank not interrupt read burst.

to interrupt read burst write command possible, more difficult. can done, if dqm signal used suppress output sdram memory controller may drive data on dq lines sdram in time write operation. because effects of dqm on read data delayed 2 cycles, effects of dqm on write data immediate, dqm must raised (to mask read data) beginning @ least 2 cycles before write command, must lowered cycle of write command (assuming write command intended have effect).

doing in 2 clock cycles requires careful coordination between time sdram takes turn off output on clock edge , time data must supplied input sdram write on following clock edge. if clock frequency high allow sufficient time, 3 cycles may required.

if read command includes auto-precharge, precharge begins same cycle interrupting command.

sdram burst ordering

a modern microprocessor cache access memory in units of cache lines. transfer 64-byte cache line requires 8 consecutive accesses 64-bit dimm, can triggered single read or write command configuring sdram chips, using mode register, perform eight-word bursts. cache line fetch typically triggered read particular address, , sdram allows critical word of cache line transferred first. ( word here refers width of sdram chip or dimm, 64 bits typical dimm.) sdram chips support 2 possible conventions ordering of remaining words in cache line.

bursts access aligned block of bl consecutive words beginning on multiple of bl. so, example, four-word burst access column address 4 7 return words 4 seven. ordering, however, depends on requested address, , configured burst type option: sequential or interleaved. typically, memory controller require 1 or other. when burst length 1 or two, burst type not matter. burst length of one, requested word word accessed. burst length of two, requested word accessed first, , other word in aligned block accessed second. following word if address specified, , previous word if odd address specified.

for sequential burst mode, later words accessed in increasing address order, wrapping start of block when end reached. so, example, burst length of four, , requested column address of five, words accessed in order 5-6-7-4. if burst length eight, access order 5-6-7-0-1-2-3-4. done adding counter column address, , ignoring carries past burst length. interleaved burst mode computes address using exclusive or operation between counter , address. using same starting address of five, four-word burst return words in order 5-4-7-6. eight-word burst 5-4-7-6-1-0-3-2. although more confusing humans, can easier implement in hardware, , preferred intel microprocessors.

if requested column address @ start of block, both burst modes (sequential , interleaved) return data in same sequential sequence 0-1-2-3-4-5-6-7. difference matters if fetching cache line memory in critical-word-first order.

sdram mode register

single data rate sdram has single 10-bit programmable mode register. later double-data-rate sdram standards add additional mode registers, addressed using bank address pins. sdr sdram, bank address pins , address lines a10 , above ignored, should 0 during mode register write.

the bits m9 through m0, presented on address lines a9 through a0 during load mode register cycle.

later (double data rate) sdram standards use more mode register bits, , provide additional mode registers called extended mode registers. register number encoded on bank address pins during load mode register command. example, ddr2 sdram has 13-bit mode register, 13-bit extended mode register #1 (emr1), , 5-bit extended mode register #2 (emr2).

auto refresh

it possible refresh ram chip opening , closing (activating , precharging) each row in each bank. however, simplify memory controller, sdram chips support auto refresh command, performs these operations 1 row in each bank simultaneously. sdram maintains internal counter, iterates on possible rows. memory controller must issue sufficient number of auto refresh commands (one per row, 4096 in example have been using) every refresh interval (tref = 64 ms common value). banks must idle (closed, precharged) when command issued.

low power modes

as mentioned, clock enable (cke) input can used stop clock sdram. cke input sampled each rising edge of clock, , if low, following rising edge of clock ignored purposes other checking cke. long cke low, permissible change clock rate, or stop clock entirely.

if cke lowered while sdram performing operations, freezes in place until cke raised again.

if sdram idle (all banks precharged, no commands in progress) when cke lowered, sdram automatically enters power-down mode, consuming minimal power until cke raised again. must not last longer maximum refresh interval tref, or memory contents may lost. legal stop clock entirely during time additional power savings.

finally, if cke lowered @ same time auto-refresh command sent sdram, sdram enters self-refresh mode. power down, sdram uses on-chip timer generate internal refresh cycles necessary. clock may stopped during time. while self-refresh mode consumes more power power-down mode, allows memory controller disabled entirely, commonly more makes difference.

sdram designed battery-powered devices offers additional power-saving options. 1 temperature-dependent refresh; on-chip temperature sensor reduces refresh rate @ lower temperatures, rather running @ worst-case rate. selective refresh, limits self-refresh portion of dram array. fraction refreshed configured using extended mode register. third, implemented in mobile ddr (lpddr) , lpddr2 deep power down mode, invalidates memory , requires full reinitialization exit from. activated sending burst terminate command while lowering cke.

ddr sdram prefetch architecture

ddr sdram employs prefetch architecture allow quick , easy access multiple data words located on common physical row in memory.

the prefetch architecture takes advantage of specific characteristics of memory accesses dram. typical dram memory operations involve 3 phases: bitline precharge, row access, column access. row access heart of read operation, involves careful sensing of tiny signals in dram memory cells; slowest phase of memory operation. however, once row read, subsequent column accesses same row can quick, sense amplifiers act latches. reference, row of 1 gbit ddr3 device 2,048 bits wide, internally 2,048 bits read 2,048 separate sense amplifiers during row access phase. row accesses might take 50 ns, depending on speed of dram, whereas column accesses off open row less 10 ns.

traditional dram architectures have long supported fast column access bits on open row. 8-bit-wide memory chip 2,048 bit wide row, accesses of 256 datawords (2048/8) on row can quick, provided no intervening accesses other rows occur.

the drawback of older fast column access method new column address had sent each additional dataword on row. address bus had operate @ same frequency data bus. prefetch architecture simplifies process allowing single address request result in multiple data words.

in prefetch buffer architecture, when memory access occurs row buffer grabs set of adjacent data words on row , reads them out ( bursts them) in rapid-fire sequence on io pins, without need individual column address requests. assumes cpu wants adjacent datawords in memory, in practice case. instance, in ddr1, 2 adjacent data words read each chip in same clock cycle , placed in pre-fetch buffer. each word transmitted on consecutive rising , falling edges of clock cycle. similarly, in ddr2 4n pre-fetch buffer, 4 consecutive data words read , placed in buffer while clock, twice faster external clock of ddr, transmits each of word in consecutive rising , falling edge of faster external clock

the prefetch buffer depth can thought of ratio between core memory frequency , io frequency. in 8n prefetch architecture (such ddr3), ios operate 8 times faster memory core (each memory access results in burst of 8 datawords on ios). 200 mhz memory core combined ios each operate 8 times faster (1600 megabits per second). if memory has 16 ios, total read bandwidth 200 mhz x 8 datawords/access x 16 ios = 25.6 gigabits per second (gbit/s), or 3.2 gigabytes per second (gb/s). modules multiple dram chips can provide correspondingly higher bandwidth.

each generation of sdram has different prefetch buffer size:

ddr sdram s prefetch buffer size 2n (two datawords per memory access)
ddr2 sdram s prefetch buffer size 4n (four datawords per memory access)
ddr3 sdram s prefetch buffer size 8n (eight datawords per memory access)
ddr4 sdram s prefetch buffer size 8n (eight datawords per memory access)




^ sdram part catalog .  070928 micron.com
^ nanya 256 mb ddr sdram datasheet (pdf). intel.com. april 2003. retrieved 2015-08-02. 
^ micron, general ddr sdram functionality, technical note, tn-46-05