Generations of SDRAM Synchronous dynamic random-access memory

1 generations of sdram

1.1 sdr sdram (single data rate synchronous dram)
1.2 ddr(1) sdram
1.3 ddr2 sdram
1.4 ddr3 sdram
1.5 ddr4 sdram
1.6 ddr5 sdram

generations of sdram

sdr sdram (single data rate synchronous dram)

this type of sdram slower ddr variants, because 1 word of data transmitted per clock cycle (single data rate). type faster predecessors edo-ram , fpm-ram took typically 2 or 3 clocks transfer 1 word of data.

ddr(1) sdram

while access latency of dram fundamentally limited dram array, dram has high potential bandwidth because each internal read row of many thousands of bits. make more of bandwidth available users, double data rate interface developed. uses same commands, accepted once per cycle, reads or writes 2 words of data per clock cycle. ddr interface accomplishes reading , writing data on both rising , falling edges of clock signal. in addition, minor changes sdr interface timing made in hindsight, , supply voltage reduced 3.3 2.5 v. result, ddr sdram not backwards compatible sdr sdram.

ddr sdram (sometimes called ddr1 greater clarity) doubles minimum read or write unit; every access refers @ least 2 consecutive words.

typical ddr sdram clock rates 133, 166 , 200 mhz (7.5, 6, , 5 ns/cycle), described ddr-266, ddr-333 , ddr-400 (3.75, 3, , 2.5 ns per beat). corresponding 184-pin dimms known pc-2100, pc-2700 , pc-3200. performance ddr-550 (pc-4400) available price.

ddr2 sdram

ddr2 sdram similar ddr sdram, doubles minimum read or write unit again, 4 consecutive words. bus protocol simplified allow higher performance operation. (in particular, burst terminate command deleted.) allows bus rate of sdram doubled without increasing clock rate of internal ram operations; instead, internal operations performed in units 4 times wide sdram. also, bank address pin (ba2) added allow 8 banks on large ram chips.

typical ddr2 sdram clock rates 200, 266, 333 or 400 mhz (periods of 5, 3.75, 3 , 2.5 ns), described ddr2-400, ddr2-533, ddr2-667 , ddr2-800 (periods of 2.5, 1.875, 1.5 , 1.25 ns). corresponding 240-pin dimms known pc2-3200 through pc2-6400. ddr2 sdram available @ clock rate of 533 mhz described ddr2-1066 , corresponding dimms known pc2-8500 (also named pc2-8600 depending on manufacturer). performance ddr2-1250 (pc2-10000) available price.

note because internal operations @ 1/2 clock rate, ddr2-400 memory (internal clock rate 100 mhz) has higher latency ddr-400 (internal clock rate 200 mhz).

ddr3 sdram

ddr3 continues trend, doubling minimum read or write unit 8 consecutive words. allows doubling of bandwidth , external bus rate without having change clock rate of internal operations, width. maintain 800–1600 m transfers/s (both edges of 400–800 mhz clock), internal ram array has perform 100–200 m fetches per second.

again, every doubling, downside increased latency. ddr sdram generations, commands still restricted 1 clock edge , command latencies given in terms of clock cycles, half speed of quoted transfer rate (a cas latency of 8 ddr3-800 8/(400 mhz) = 20 ns, same latency of cas2 on pc100 sdr sdram).

ddr3 memory chips being made commercially, , computer systems using them available second half of 2007, significant usage 2008 onwards. initial clock rates 400 , 533 mhz, described ddr3-800 , ddr3-1066 (pc3-6400 , pc3-8500 modules), 667 , 800 mhz, described ddr3-1333 , ddr3-1600 (pc3-10600 , pc3-12800 modules) common. performance ddr3-2800 (pc3 22400 modules) available price.

ddr4 sdram

ddr4 sdram successor ddr3 sdram. revealed @ intel developer forum in san francisco in 2008, , due released market during 2011. timing has varied considerably during development - expected released in 2012, , later (during 2010) expected released in 2015, before samples announced in 2011 , manufacturers began announce commercial production , release market anticipated in 2012. ddr4 expected reach mass market adoption around 2015, comparable approximately 5 years taken ddr3 achieve mass market transition on ddr2.

the new chips expected run @ 1.2 v or less, versus 1.5 v of ddr3 chips, , have in excess of 2 billion data transfers per second. expected introduced @ frequency rates of 2133 mhz, estimated rise potential 4266 mhz , lowered voltage of 1.05 v 2013.

ddr4 not double internal prefetch width again, use same 8n prefetch ddr3. thus, necessary interleave reads several banks keep data bus busy.

in february 2009, samsung validated 40 nm dram chips, considered significant step towards ddr4 development since of 2009, current dram chips beginning migrate 50 nm process. in january 2011, samsung announced completion , release testing of 30 nm 2 gb ddr4 dram module. has maximum bandwidth of 2.13 gbit/s @ 1.2 v, uses pseudo open drain technology , draws 40% less power equivalent ddr3 module.

ddr5 sdram

in march 2017, jedec announced ddr5 standard under development, provided no details except goals of doubling bandwidth of ddr4, reducing power consumption, , publishing standard in 2018.