SDRAM control signals Synchronous dynamic random-access memory

1 sdram control signals

1.1 command signals
1.2 bank selection (ban)
1.3 addressing (a10/an)
1.4 commands

sdram control signals

all commands timed relative rising edge of clock signal. in addition clock, there 6 control signals, active low, sampled on rising edge of clock:

cke clock enable. when signal low, chip behaves if clock has stopped. no commands interpreted , command latency times not elapse. state of other control lines not relevant. effect of signal delayed 1 clock cycle. is, current clock cycle proceeds usual, following clock cycle ignored, except testing cke input again. normal operations resume on rising edge of clock after 1 cke sampled high.put way, other chip operations timed relative rising edge of masked clock. masked clock logical , of input clock , state of cke signal during previous rising edge of input clock.
cs chip select. when signal high, chip ignores other inputs (except cke), , acts if nop command received.
dqm data mask. (the letter q appears because, following digital logic conventions, data lines known dq lines.) when high, these signals suppress data i/o. when accompanying write data, data not written dram. when asserted high 2 cycles before read cycle, read data not output chip. there 1 dqm line per 8 bits on x16 memory chip or dimm.

command signals

ras row address strobe. despite name, not strobe, rather command bit. along cas , we, selects 1 of 8 commands.
cas column address strobe. despite name, not strobe, rather command bit. along ras , we, selects 1 of 8 commands.
we write enable. along ras , cas, selects 1 of 8 commands. distinguishes read-like commands write-like commands.

bank selection (ban)

sdram devices internally divided either 2, 4 or 8 independent internal data banks. 1 3 bank address inputs (ba0, ba1 , ba2) used select bank command directed toward.

addressing (a10/an)

many commands use address presented on address input pins. commands, either not use address, or present column address, use a10 select variants.

commands

the commands defined follows:

all sdram generations (sdr , ddrx) use same commands, changes being:

additional address bits support larger devices
additional bank select bits
wider mode registers (ddr2 , use 13 bits, a0–a12)
additional extended mode registers (selected bank address bits)
ddr2 deletes burst terminate command; ddr3 reassigns zq calibration
ddr3 , ddr4 use a12 during read , write command indicate burst chop , half-length data transfer
ddr4 changes encoding of activate command. new signal act controls it, during other control lines used row address bits 16, 15 , 14. when act high, other commands same above.