Generations of SDRAM Synchronous dynamic random-access memory
1 generations of sdram 1.1 sdr sdram (single data rate synchronous dram) 1.2 ddr(1) sdram 1.3 ddr2 sdram 1.4 ddr3 sdram 1.5 ddr4 sdram 1.6 ddr5 sdram generations of sdram sdr sdram (single data rate synchronous dram) this type of sdram slower ddr variants, because 1 word of data transmitted per clock cycle (single data rate). type faster predecessors edo-ram , fpm-ram took typically 2 or 3 clocks transfer 1 word of data. ddr(1) sdram while access latency of dram fundamentally limited dram array, dram has high potential bandwidth because each internal read row of many thousands of bits. make more of bandwidth available users, double data rate interface developed. uses same commands, accepted once per cycle, reads or writes 2 words of data per clock cycle. ddr interface accomplishes reading , writing data on both rising , falling edges of clock signal. in addition, minor changes sdr interface timing made in hindsight, , supply voltage reduced 3.3 2.5 v. result, ddr sdram not backwards co