SDR SDRAM Synchronous dynamic random-access memory
1 sdr sdram 1.1 sdram control signals 1.1.1 command signals 1.1.2 bank selection (ban) 1.1.3 addressing (a10/an) 1.1.4 commands 1.2 sdram construction , operation 1.3 command interactions 1.3.1 interrupting read burst 1.4 sdram burst ordering 1.5 sdram mode register 1.6 auto refresh 1.7 low power modes 1.8 ddr sdram prefetch architecture sdr sdram the 64 mb of sound memory on sound blaster x-fi fatality pro sound card built 2 micron 48lc32m8a2 sdram chips. run @ 133 mhz (7.5 ns clock period) , have 8-bit wide data buses. originally known sdram, single data rate sdram can accept 1 command , transfer 1 word of data per clock cycle. typical clock frequencies 100 , 133 mhz. chips made variety of data bus sizes (most commonly 4, 8 or 16 bits), chips assembled 168-pin dimms read or write 64 (non-ecc) or 72 (ecc) bits @ time. use of data bus intricate , requires complex dram controller circuit. because data written dram must presented in same cycle write command, reads produce output 2 or 3 c